HW-V5-ML555-G【PDF 25/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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Table 3-1:

Edge Connector for PCI Express Operation

P13 Edge Connector Socket Pinout for PCI Express Designs (Continued)

P13 A Side

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

Signal

PERN3

GND

RESERVED

RESERVED

GND

PERP4

PERN4

GND

GND

PERP5

PERN5

GND

GND

PERP6

PERN6

GND

GND

PERP7

PERN7

GND

P13 B Side

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

Signal

RESERVED

PCIE_PRSNT2_B (1)

GND

PETP4

PETN4

GND

GND

PETP5

PETN5

GND

GND

PETP6

PETN6

GND

GND

PETP7

PETN7

GND

PCIE_PRSNT2_B (1)

GND

Notes:

1. PCIE_PRSNT1_B can be connected to one of three PCIE_PRSNT2_B signals by connecting a shunt on

connector P45. See Table 3-2 for application information.

2. No connect on the ML555 board.

3. The ML555 board layout provides two methods of interfacing the PCIE_REFCLK to the FPGA. The

default method is to AC couple the 100 MHz PCIE_REFCLK directly to the GTP_DUAL tile X0Y2

MGTREFCLK input pins. An alternative method is to remove two 0 Ω resistors and install an

ICS874003-02 PCI Express Jitter attenuator module, which provides a 100, 125, or 250 MHz reference

clock to the GTP transceiver. The jitter attentuator has two LVDS outputs that connect to the GTP and

FPGA global clock inputs. One of the jitter attentuator LVDS outputs is connected to the MGTREFCLK

inputs of GTP_DUAL tile X0Y2 for PCI Express lanes 0 and 1. The PCIE_REFCLK is also connected to

the FPGA global clock network on pins J16 and J17. Internal FPGA clock buffers distribute this clock to

other GTP_DUAL tiles for PCI Express operation. The architecture of the FPGA permits an external

MGTREFCLK to be driven a maximum of three GTP_DUAL tiles up or down. See “Serial Bus Clocking

with Optional ICS874003-02 Clock Jitter Attenuator (PCI Express Operation),” page 60 for additional

information.

4. The PETPX and PETNX pins connect to the PCI Express transmitter differential pair on the system

board and the PCI Express receiver on the add-in card.

5. The PERPX and PERNX pins connect to the PCI Express receiver differential pair on the system board

and the PCI Express transmitter on the add-in card.

6. PCIE_PERST connects to FPGA pin AE14.

The PCI Express Card Electromechanical Specification requires add-in cards to implement

variable-length edge finger pads and tie PRSNT1_B and PRSNT2_B signals together on the

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

25

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